| CPC H01L 21/7682 (2013.01) [H10B 12/315 (2023.02); H10B 12/482 (2023.02)] | 13 Claims |

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1. A semiconductor structure, comprising:
a substrate, bit line structures located on the substrate, and capacitor contact holes located on each of two opposite sides of the bit line structure;
isolation side walls, each of which is located between a respective bit line structure and the capacitor contact holes on one side of the bit line structure, wherein a gap isolation layer is provided between the isolation side walls located on two opposite sides of the bit line structure; the gap isolation layer is located on the bit line structure, and a first gap is provided inside the gap isolation layer; and a second gap is provided between one of the isolation side walls and the gap isolation layer; wherein
a top surface of the gap isolation layer is lower than a top surface of the isolation side wall.
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6. A method for manufacturing a semiconductor structure, comprising:
providing a substrate and bit line structures located on the substrate, wherein each of the bit line structures comprises a top dielectric layer, and is provided with capacitor contact holes in each of two opposite sides of the bit line structure;
forming a sacrificial side wall covering a side wall of the top dielectric layer;
removing at least part of the top dielectric layer to form a first gap;
performing a deposition process to form a gap isolation layer with the first gap; and
forming an isolation side wall covering the sacrificial side wall, and removing at least part of the sacrificial side wall to form a second gap located between the isolation side wall and the gap isolation layer;
wherein
a top surface of the gap isolation layer is lower than a top surface of the isolation side wall;
and
after the second gap is formed, a second sealing layer that blocks a top opening of the second gap is formed; and the second sealing layer covers the top surface of the gap isolation layer.
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