US 12,237,213 B2
Method for manufacturing semiconductor device
Libin Zhang, Beijing (CN); Yayi Wei, Beijing (CN); and Zhen Song, Beijing (CN)
Assigned to Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
Appl. No. 17/631,932
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
PCT Filed Nov. 12, 2021, PCT No. PCT/CN2021/130254
§ 371(c)(1), (2) Date Feb. 1, 2022,
PCT Pub. No. WO2023/065432, PCT Pub. Date Apr. 27, 2023.
Claims priority of application No. 202111228704.0 (CN), filed on Oct. 21, 2021.
Prior Publication US 2024/0038584 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 29/40 (2006.01); G03F 7/09 (2006.01)
CPC H01L 21/76802 (2013.01) [H01L 21/76877 (2013.01); H01L 29/401 (2013.01); G03F 7/094 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, wherein:
the semiconductor device comprises a substrate and a to-be-connected structure disposed on a side of the substrate; and
the method comprises:
forming a photolithographic coating on the to-be-connected structure, wherein the photolithographic coating comprises a first film, a photolithographic film, and a second film which are stacked in the above-listed sequence, and refractive indexes of the first film and the second film are smaller than 1;
exposing the photolithographic coating to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film;
exposing the photolithographic coating to a light having a second wavelength through a mask, to image a pattern of the mask to a second region of the photolithographic film; and
forming an electrical connection in contact with the to-be-connected structure at a connection region, wherein the connection region is a region in which the first region and the second region overlap.