US 12,237,207 B2
Method for forming a buried metal line in a semiconductor substrate
Boon Teik Chan, Wilsele (BE); Zheng Tao, Heverlee (BE); Efrain Altamirano Sanchez, Kessel-Lo (BE); Anshul Gupta, Leuven (BE); and Basoene Briggs, Heverlee (BE)
Assigned to Imec vzw, Leuven (BE)
Filed by IMEC VZW, Leuven (BE)
Filed on Sep. 18, 2023, as Appl. No. 18/469,374.
Application 18/469,374 is a division of application No. 16/934,200, filed on Jul. 21, 2020, abandoned.
Claims priority of application No. 19187988 (EP), filed on Jul. 24, 2019.
Prior Publication US 2024/0006228 A1, Jan. 4, 2024
Int. Cl. H01L 21/74 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/743 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for forming a buried metal line in a semiconductor substrate, the method comprising:
conformally depositing a first liner over the semiconductor substrate;
depositing a spacer layer over the first liner;
forming, in the semiconductor substrate and at a level below a base of each semiconductor structure, a trench between a pair of semiconductor structures that protrude from the semiconductor substrate;
conformally depositing a second liner over the semiconductor substrate;
conformally depositing a barrier layer over the second liner;
selectively removing the barrier layer outside of the trench, wherein the barrier layer in the trench is disposed on the second liner;
selectively depositing a metal line material in the trench to thereby form a metal line in the trench, wherein the barrier layer is configured to promote deposition of the metal material in the trench, and wherein the second liner is configured to inhibit deposition of the metal material outside of the trench;
subsequent to selectively depositing the metal line material, conformally depositing a continuous capping liner over the metal line material and the pair of semiconductor structures; and
embedding the pair of semiconductor structures in an insulating layer.