US 12,237,188 B2
Machine learning on overlay management
Tzu-Cheng Lin, Hsinchu (TW); Y. Y. Peng, Hsinchu (TW); Jerry Wang, Hsinchu (TW); Kewei Zuo, Hsinchu (TW); and Chien Rhone Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 14, 2023, as Appl. No. 18/183,491.
Application 18/183,491 is a continuation of application No. 17/178,929, filed on Feb. 18, 2021, granted, now 11,626,304.
Application 17/178,929 is a continuation of application No. 16/405,702, filed on May 7, 2019, granted, now 10,964,566, issued on Mar. 30, 2021.
Claims priority of provisional application 62/692,208, filed on Jun. 29, 2018.
Prior Publication US 2023/0223287 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G05B 19/19 (2006.01); G03F 7/00 (2006.01); G05B 13/02 (2006.01); H01L 21/67 (2006.01)
CPC H01L 21/67259 (2013.01) [G03F 7/70633 (2013.01); G05B 13/027 (2013.01); G05B 19/19 (2013.01); G05B 2219/32335 (2013.01); G05B 2219/45028 (2013.01); G05B 2219/45031 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A computing system, comprising:
a processor; and
a storage unit having executable instructions stored thereon which, when executed by the processor, configures the processor to implement actions including:
receiving, by a computing device, a function correlating one or more of a tool position or an item position on a first side of the function with an overlay metrology on a second side of the function;
receiving, by the computing device, a first tool position of the tool with respect to forming a first feature on a first wafer and a first item position of a first portion of the first wafer corresponding to the forming the first feature;
estimating, by the computing device, a first overlay metrology of the first feature on the first wafer based on the function, the first tool position and the first item position; and
adjusting, by a controller coupled to the computing system, one or more of the first tool position or the first item position in a semiconductor manufacturing process of forming the first feature on the first wafer based on the estimated first overlay metrology.