US 12,237,175 B2
Polymerization protective liner for reactive ion etch in patterning
Bhaskar Nagabhirava, Cohoes, NY (US); Phillip Friddle, Clifton Park, NY (US); Michael Goss, Holliston, MA (US); Yann Mignot, Slingerlands, NY (US); and Dominik Metzler, Saratoga Springs, NY (US)
Assigned to Lam Research Corporation, Fremont, CA (US); and International Business Machines Corporation, Armonk, NY (US)
Appl. No. 17/596,189
Filed by Lam Research Corporation, Fremont, CA (US); and International Business Machines Corporation, Armonk, NY (US)
PCT Filed Jun. 3, 2020, PCT No. PCT/US2020/070118
§ 371(c)(1), (2) Date Dec. 3, 2021,
PCT Pub. No. WO2020/247977, PCT Pub. Date Dec. 10, 2020.
Claims priority of provisional application 62/857,190, filed on Jun. 4, 2019.
Prior Publication US 2022/0238349 A1, Jul. 28, 2022
Int. Cl. H01L 21/311 (2006.01); H01L 21/67 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/31144 (2013.01) [H01L 21/31116 (2013.01); H01L 21/67069 (2013.01); H01L 21/76802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a semiconductor substrate to a chamber, the semiconductor substrate having a target layer having a thickness t and a metallization layer underlying the target layer with at least one region comprising metal;
forming a lower patterned mask layer over the target layer by etching a lower mask layer;
forming a polymerization protective liner over the lower patterned mask layer without breaking vacuum;
forming an upper mask layer over the polymerization protective liner; and
patterning the semiconductor substrate using the upper mask layer to form at least one via.