	US 12,237,171 B1
	Method of forming vanadium nitride layer and structure including the vanadium nitride layer
Giuseppe Alessio Verni, Ottignies (BE); Qi Xie, Wilsele (BE); Henri Jussila, Espoo (FI); Charles Dezelah, Helsinki (FI); Jiyeon Kim, Phoenix, AZ (US); Eric James Shero, Phoenix, AZ (US); and Paul Ma, Scottsdale, AZ (US)
Assigned to ASM IP Holding B.V., Almere (NL)
Filed by ASM IP Holding B.V., Almere (NL)
Filed on Oct. 12, 2023, as Appl. No. 18/379,228.
Application 18/379,228 is a continuation of application No. 17/113,242, filed on Dec. 7, 2020, granted, now 11,885,013.
Claims priority of provisional application 62/949,307, filed on Dec. 17, 2019.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/285 (2006.01); H01L 29/49 (2006.01)

CPC H01L 21/28556 (2013.01) [H01L 29/4966 (2013.01)]

10 Claims

1. A method of forming a gate electrode structure, the method comprising the steps of:

providing a substrate within a reaction chamber of a reactor; and

using a cyclical deposition process, depositing a vanadium nitride layer onto a surface of the substrate,

wherein a cycle of the cyclical deposition process consists of:

providing a vanadium precursor to the reaction chamber; and

providing a nitrogen reactant to the reaction chamber, and

purging the chamber using a vacuum and/or an inert gas, and

wherein the cyclical deposition process comprises continuously providing the vanadium precursor and periodically providing the nitrogen reactant.