US 12,237,165 B2
Method for wafer bonding including edge trimming
Yung-Lung Lin, Taichung (TW); Hau-Yi Hsiao, Chiayi (TW); Chih-Hui Huang, Tainan County (TW); Kuo-Hwa Tzeng, Taipei (TW); and Cheng-Hsien Chou, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 30, 2021, as Appl. No. 17/390,520.
Application 17/390,520 is a continuation of application No. 16/685,577, filed on Nov. 15, 2019, granted, now 11,087,971.
Application 16/685,577 is a continuation of application No. 15/922,296, filed on Mar. 15, 2018, granted, now 10,504,716, issued on Dec. 10, 2019.
Prior Publication US 2021/0358740 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); H01L 21/18 (2006.01); H01L 21/20 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01)
CPC H01L 21/02021 (2013.01) [H01L 21/02035 (2013.01); H01L 21/02052 (2013.01); H01L 21/02532 (2013.01); H01L 21/187 (2013.01); H01L 21/2007 (2013.01); H01L 21/30625 (2013.01); H01L 21/76251 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for wafer bonding, comprising:
forming an epitaxial layer on a top surface of a first wafer;
forming a sacrificial layer over the epitaxial layer;
trimming an edge of the first wafer prior to bonding the first wafer to a second wafer;
removing the sacrificial layer;
forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer; and
bonding the top surface of the first wafer to the second wafer.