US 12,237,110 B2
Electronic component
Mitsuru Ikeda, Nagaokakyo (JP); and Yasuhiro Nishisaka, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Dec. 11, 2023, as Appl. No. 18/534,790.
Application 18/534,790 is a continuation of application No. 17/752,910, filed on May 25, 2022, granted, now 11,869,716.
Claims priority of application No. 2021-091546 (JP), filed on May 31, 2021.
Prior Publication US 2024/0105386 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01G 2/06 (2006.01); H01G 4/008 (2006.01); H01G 4/12 (2006.01); H01G 4/232 (2006.01); H01G 4/248 (2006.01); H01G 4/30 (2006.01)
CPC H01G 2/06 (2013.01) [H01G 4/008 (2013.01); H01G 4/1227 (2013.01); H01G 4/2325 (2013.01); H01G 4/248 (2013.01); H01G 4/30 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An electronic component comprising:
an electronic element; and
an interposer board; wherein
the electronic element includes:
a multilayer body including dielectric layers and internal electrode layers which are laminated, a pair of multilayer body end surfaces intersecting the internal electrode layers, a pair of multilayer body side surfaces intersecting the multilayer body end surfaces, and a pair of main surfaces intersecting the multilayer body end surfaces and the multilayer body side surfaces; and
external electrodes each on a respective one of the pair of multilayer body end surfaces and connected to the internal electrode layers;
the interposer board includes a pair of board end surfaces, a pair of board side surfaces intersecting the board end surfaces, and a pair of board main surfaces intersecting the board end surfaces and the board side surfaces;
one of the pair of board main surfaces is joined with one of the pair of multilayer body main surfaces or with one of the pair of multilayer body side surfaces;
the interposer board is an alumina board; and
the pair of board end surfaces include a metal layer including a Pd-containing layer, and an electrolessly-plated Cu layer on an outer periphery of the Pd-containing layer.