| CPC G11C 8/10 (2013.01) [G11C 7/02 (2013.01); G11C 8/14 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] | 19 Claims |
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1. An integrated circuit, comprising:
a memory cell array;
a row decoder configured to generate a first decoder signal;
a column decoder configured to generate a second decoder signal; and
an array of write assist circuits electrically coupled to the row decoder, the column decoder and the memory cell array, each write assist circuit being configured to set an operating voltage of a corresponding memory cell, and the operating voltage corresponds to an output signal, each write assist circuit being configured to generate the output signal at least in response to a first control signal, each write assist circuit comprises:
an AND gate;
a first P-type transistor coupled to the AND gate, wherein a first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate, a second terminal of the first P-type transistor is configured as a first output node to send the output signal to the corresponding memory cell in response to the AND signal and a third terminal of the first P-type transistor is coupled to a supply voltage; and
a programmable voltage tuner coupled to the first P-type transistor, the programmable voltage tuner comprising:
a set of P-type transistors coupled together in parallel, and configured to receive a set of select control signals, wherein the set of P-type transistors are coupled to the first P-type transistor;
wherein the AND gate comprises:
a NAND gate; and
an inverter coupled to the NAND gate and the first P-type transistor.
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