| CPC G11C 7/1045 (2013.01) [G11C 7/1063 (2013.01); G11C 7/222 (2013.01)] | 21 Claims |
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1. A semiconductor memory device comprising:
a first chip;
a second chip; and
a third chip connectable to a first device, the third chip being connected to the first chip via a first channel and connected to the second chip via a second channel, the third chip being configured to:
receive a first command sequence to request status information from the first device, the first command sequence including at least a first address indicating the first chip,
in accordance with receiving first command sequence, perform transfer of a second command sequence including the first address via the first channel and transfer of a third command sequence including a second address indicating the second chip via the second channel,
transfer first read enable signals to the first channel and the second channel in parallel after a first time elapses from completion of the transfers of the second command sequence and the third command sequence, and acquire pieces of first status information in parallel via the first channel and the second channel, and
output the first status information to the first device on the basis of a second read enable signal in a case where the second read enable signal is received from the first device.
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