US 12,237,040 B2
Method and apparatus to perform a read of a column in a memory accessible by row and/or by column
Sourabh Dongaonkar, Portland, OR (US); Chetan Chauhan, Folsom, CA (US); Jawad B. Khan, Portland, OR (US); Sandeep K. Guliani, Folsom, CA (US); and William K. Waller, Eagle, ID (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 7, 2021, as Appl. No. 17/468,210.
Prior Publication US 2021/0407564 A1, Dec. 30, 2021
Int. Cl. G11C 7/10 (2006.01); G11C 5/02 (2006.01); G11C 5/14 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 5/025 (2013.01); G11C 5/141 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a non-volatile memory comprising a cross-point memory array having a plurality of rows and columns of memory cells to store an array of bits, each column to store a multi-bit entry; and
circuitry to cause storage of the multi-bit entries in a logical column in the cross-point memory array diagonally across N rows and N columns in the cross-point memory array with each multi-bit entry in the logical column stored at a different physical row address and a different physical column address.