an error correction code (ECC) circuit configured to receive a data burst and generate first ECC data or second ECC data; and

a processor configured to control operations of the ECC circuit,

wherein the ECC circuit comprises:

an ECC select circuit configured to select and output one of first ECC conversion data and second ECC conversion data, based on an ECC select signal received from an outside of the memory controller; and

an ECC conversion circuit configured to:

generate the first ECC data by encoding the data burst based on the first ECC conversion data, or

generate the second ECC data by encoding the data burst based on the second ECC conversion data, and

wherein the second ECC conversion data is set to be capable of correcting an error generated in one or more preset protected bits among bits included in each of pieces of partial data included in the data burst.