US 12,237,033 B2
Component overprovisioning in layered devices
Domenico Balzano, Torre Annunziata (IT); and Enrico Camillo Beretta, Sengkang (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2022, as Appl. No. 17/664,342.
Prior Publication US 2023/0377674 A1, Nov. 23, 2023
Int. Cl. G11C 29/44 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/44 (2013.01) [G11C 29/52 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A test device, comprising:
one or more components configured to:
perform, on a set of memory components of a memory device, a set of production tests;
identify, based on the set of production tests, a failure of a memory component of the memory device; and
reconfigure the memory device to downsize the memory device from a first configuration associated with the set of memory components to a second configuration associated with a first subset of memory components in the set of memory components, a second subset of memory components in the set of memory components, and a third subset of memory components in the set of memory components, wherein:
the first subset of memory components includes one or more active memory components;
a memory density associated with the second configuration is based on the first subset of memory components;
the second subset of memory components includes the failed memory component;
the third subset of memory components includes one or more redundant memory components; and
the first subset of memory components, the second subset of memory components, and the third subset of memory components are different.