US 12,237,031 B2
Refresh rate selection for a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2022, as Appl. No. 17/807,307.
Claims priority of provisional application 63/365,629, filed on Jun. 1, 2022.
Prior Publication US 2023/0395174 A1, Dec. 7, 2023
Int. Cl. G11C 29/12 (2006.01)
CPC G11C 29/12015 (2013.01) 25 Claims
OG exemplary drawing
 
20. A method, comprising:
reading one or more bits that are stored in a mode register of a memory device and that indicate a test parameter to be used during a first time period in which a memory built-in self-test is to be performed,
wherein the test parameter indicates a refresh rate or a timing property that is to be used for memory cells of the memory device during the first time period in which the memory built-in self-test is to be performed;
performing the memory built-in self-test during the first time period and in accordance with the test parameter;
identifying a non-test parameter to be used during a second time period,
wherein the non-test parameter indicates a non-test refresh rate that is to be used while performing one or more read or write operations using the memory cells during the second time period, wherein the non-test refresh rate indicates a rate at which the memory cells are to be refreshed while the one or more read or write operations are being performed; and
performing the one or more read or write operations, using the memory cells, during the second time period and after performing the memory built-in self-test, wherein the one or more read or write operations are performed according to the non-test parameter.