US 12,237,029 B2
Testing method and testing system
Bo Jung Peng, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Nov. 15, 2022, as Appl. No. 18/055,422.
Prior Publication US 2024/0161847 A1, May 16, 2024
Int. Cl. G11C 29/10 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01)
CPC G11C 29/10 (2013.01) [G01R 31/2837 (2013.01); G01R 31/31725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A testing method, comprising:
inputting a first signal to a memory chip;
putting the memory chip into a self-refresh mode according to the first signal;
inputting an active command to test the memory chip so as to generate a first testing result according to the first signal, wherein an input time of the active command must be when the first signal is at a high electrical potential;
adjusting a bandwidth of the first signal to generate a second signal so as to input to the memory chip;
putting the memory chip into the self-refresh mode according to the second signal;
inputting the active command to test the memory chip so as to generate a second testing result according to the second signal, wherein the input time of the active command must be when the second signal is at a high electrical potential; and
calculating a self-refresh rate of the memory chip according to the first testing result and the second testing result.