US 12,237,028 B2
Memory circuit and method of operating same
Chun-Hao Chang, Hsinchu (TW); Gu-Huan Li, Hsinchu (TW); and Shao-Yu Chou, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 29, 2023, as Appl. No. 18/522,564.
Application 18/522,564 is a continuation of application No. 18/155,925, filed on Jan. 18, 2023, granted, now 11,862,264.
Application 18/155,925 is a continuation of application No. 17/319,582, filed on May 13, 2021, granted, now 11,568,948, issued on Jan. 31, 2023.
Claims priority of provisional application 63/149,112, filed on Feb. 12, 2021.
Prior Publication US 2024/0096431 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 17/18 (2006.01); G11C 17/16 (2006.01)
CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a non-volatile memory cell;
a comparator coupled to the non-volatile memory cell, and configured to generate a first output signal, the comparator comprising a first input terminal and a first output terminal, the first input terminal of the comparator being coupled to the non-volatile memory cell by a first node, and being configured to receive a first voltage, and the first output terminal of the comparator being configured to output the first output signal; and
a detection circuit coupled to the comparator and the non-volatile memory cell, the detection circuit configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator, the detection circuit comprising:
a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.