| CPC G11C 17/16 (2013.01) [G11C 16/0433 (2013.01); G11C 16/24 (2013.01)] | 19 Claims |
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1. An anti-fuse memory, comprising:
at least one anti-fuse memory cell, wherein the anti-fuse memory cell comprises:
an isolation structure, disposed in a substrate;
a select gate, disposed on the substrate;
a first gate insulating layer, disposed between the select gate and the substrate;
an anti-fuse gate, disposed on the substrate and partially overlapped with the isolation structure;
a second gate insulating layer, disposed between the anti-fuse gate and the substrate;
a first doped region and a second doped region, disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate; and
a third doped region, disposed in the substrate and located between the first doped region and the isolation structure,
wherein the third doped region is in contact with the first doped region and the isolation structure.
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