US 12,237,024 B2
Memory device and programming method thereof
Kun-Tse Lee, Hsinchu County (TW); Han-Sung Chen, Hsinchu (TW); and Shih-Chang Huang, Penghu County (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Aug. 24, 2022, as Appl. No. 17/894,838.
Prior Publication US 2024/0071523 A1, Feb. 29, 2024
Int. Cl. G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/28 (2013.01)] 19 Claims
OG exemplary drawing
 
10. A memory device, comprising:
a memory cell array, comprising a plurality of memory blocks, wherein each of the memory blocks has a plurality of memory pages; and
a controller, coupled to the memory cell array and used to:
according to a step value, based on an incremental step pulse programming scheme, perform a plurality of programming operations for a selected memory page;
in a setting mode, respectively perform a plurality of program verify operations corresponding to the programming operations to respectively generate a plurality of pass bit numbers;
in the setting mode, calculate a pass bit number difference value of two pass bit numbers corresponding to two programming operations; and
in the setting mode, adjust an amount of the step value according to the pass bit number difference value,
wherein the controller comprises:
a timer, used to set a width of a programming pulse of each of the programming operations; and
a failure bit detector, generating the pass bit numbers corresponding to the program verify operations according to a plurality of read data corresponding to the program verify operations.