US 12,237,022 B2
Semiconductor device for improving retention performance and operating method thereof
Sanggyu Ko, Suwon-si (KR); and Yeongmin Yoo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 9, 2022, as Appl. No. 17/983,705.
Claims priority of application No. 10-2021-0156075 (KR), filed on Nov. 12, 2021; and application No. 10-2022-0082135 (KR), filed on Jul. 4, 2022.
Prior Publication US 2023/0154551 A1, May 18, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/3404 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a memory including a plurality of blocks; and
a controller configured to perform an erase operation on at least one block of the memory, perform a correction operation on a threshold voltage of a deep-erased cell among a plurality of cells of the at least one block, and perform an erase verify operation by identifying whether threshold voltages of the plurality of cells fall within a predefined range,
wherein the controller is further configured to, in the correction operation, turn off a string select line and a ground select line of the at least one block and apply a correction voltage to word lines of the at least one block.