| CPC G11C 16/26 (2013.01) [G06F 3/0658 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3404 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/50004 (2013.01)] | 20 Claims |

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1. A memory system comprising:
a semiconductor memory including a plurality of memory cells each configured to store data having one of at least a first value and a second value according to a threshold voltage thereof, the first value corresponding to the threshold voltage included in a first voltage range, and the second value corresponding to the threshold voltage included in a second voltage range; and
a controller configured to
write data having the first value in each of a plurality of first memory cells among the plurality of memory cells,
write data having the second value in each of a plurality of second memory cells among the plurality of memory cells,
determine a first voltage by executing a tracking process for the plurality of memory cells, and
read data from the plurality of memory cells using the first voltage in a read process after the tracking process,
wherein the controller is configured to, in the tracking process,
perform a plurality of read operations using a plurality of read voltages in a third voltage range, the third voltage range including a part of the first voltage range and a part of the second voltage range, to determine a first threshold voltage distribution of the plurality of memory cells,
estimate a second threshold voltage distribution of the plurality of first memory cells in the third voltage range based on the first threshold voltage distribution,
calculate a third threshold voltage distribution of the plurality of second memory cells in the third voltage range based on a difference between the first threshold voltage distribution and the second threshold voltage distribution, and
determine a voltage that is within the third voltage range as the first voltage, based on the second threshold voltage distribution and the third threshold voltage distribution.
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