US 12,237,020 B2
Storing bits with cells in a memory device
Daniele Vimercati, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/888,298.
Prior Publication US 2024/0055056 A1, Feb. 15, 2024
Int. Cl. G11C 11/22 (2006.01); G11C 13/00 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 11/2259 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 16/12 (2013.01)] 22 Claims
OG exemplary drawing
 
11. An apparatus, comprising:
a first switching component coupled with a first digit line and configured to couple the first digit line with a second digit line and a first input of a sense component;
a second switching component coupled with the second digit line and configured to couple the second digit line with the first digit line and the first input of the sense component;
a third switching component coupled with a third digit line and configured to couple the third digit line with a fourth digit line and with a second input of the sense component; and
a fourth switching component coupled with the fourth digit line and configured to couple the fourth digit line with the third digit line and the second input of the sense component.