US 12,237,018 B2
Memory sub-system sanitization
Eric N. Lee, San Jose, CA (US); Robert W. Strong, Folsom, CA (US); William Akin, Morgan Hill, CA (US); and Jeremy Binfet, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 3, 2023, as Appl. No. 18/386,919.
Application 18/386,919 is a continuation of application No. 17/458,795, filed on Aug. 27, 2021, granted, now 11,810,621.
Prior Publication US 2024/0062828 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
increasing a source line voltage for a plurality of memory blocks of a memory device to a sanitization voltage; and
applying the sanitization voltage to the plurality of memory blocks of the memory device, wherein the sanitization voltage is greater than an erase voltage of the plurality of memory blocks.