| CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); H01L 23/528 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 16 Claims |
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1. A semiconductor memory device, comprising:
a bit line extending in a first direction;
a first signal line extending in the first direction;
a second signal line extending in the first direction, and arranged at one side of the first signal line in a second direction, the second crossing the first direction;
a third signal line extending in the first direction, and arranged at one side of the second signal line in the second direction;
a fourth signal line extending in the first direction, and arranged at one side of the third signal line in the second direction;
a source line;
a memory cell unit including
a first selection transistor connected to the bit line,
a second selection transistor connected to the source line, and
a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including:
a first memory cell,
a second memory cell located between the first selection transistor and the first memory cell,
a third memory cell located between the first selection transistor and the second memory cell, and
a fourth memory cell located between the first selection transistor and the third memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a third word line connected to the third memory cell;
a fourth word line connected to the fourth memory cell;
a driver circuit configured to apply voltages to the first to the fourth signal lines;
a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the first signal line, the first diffused layer and the second diffused layer are arranged along the first direction;
a second transistor including a third diffused layer connected to the second word line and a fourth diffused layer connected to the second signal line, arranged at one side of the first transistor in the second direction, the third diffused layer and the fourth diffused layer are arranged along the first direction;
a third transistor including a fifth diffused layer connected to the third word line and a sixth diffused layer connected to the third signal line, arranged at one side of the second transistor in the second direction, the fifth diffused layer and the sixth diffused layer are arranged along the first direction; and
a fourth transistor including a seventh diffused layer connected to the fourth word line and an eighth diffused layer connected to the fourth signal line, arranged at one side of the third transistor in the second direction, the seventh diffused layer and the eighth diffused layer are arranged along the first direction,
wherein
the first word line includes
a first part extending in the second direction above the second transistor,
a second part extending in the second direction above the third transistor and
a third part extending in the second direction above the fourth transistor,
the second word line includes
a fourth part extending in the second direction above the third transistor and
a fifth part extending in the second direction above the fourth transistor, and
the third word line includes
a sixth part extending in the second direction above the fourth transistor, and
wherein
the second part of the first word line and the fourth part of the second word line are arranged in the first direction with a first interval, and
the third part of the first word line, the fifth part of the second word line and the sixth part of the third word line are arranged in the first direction with the first intervals.
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