a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, respective ones of the plurality of vector-by-matrix multiplication comprising an array of non-volatile memory cells organized into rows and columns, wherein the plurality of vector-by-matrix multiplication arrays share control gate lines and source lines;

a shared high voltage row decoder coupled to the control gate lines and the source lines of the plurality of vector-by-matrix multiplication arrays to apply a first set of voltages to control gate terminals, source line terminals, and erase gate terminals of one or more selected rows in the plurality of vector-by-matrix multiplication arrays during a program operation;

a plurality of read row decoders, each read row decoder coupled to read word lines and word line terminals of one of the arrays in the plurality of vector-by-matrix multiplication arrays but not the other arrays in the plurality of vector-by-matrix multiplication arrays to apply a second voltage lower than each of the first set of voltages to word line terminals of one or more selected rows in the one of the arrays during a read operation; and

a shared program row decoder coupled to all of the arrays in the plurality of vector-by-matrix multiplication arrays to apply a third voltage lower than each of the first set of voltages to word line terminals of one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation;

wherein the read word lines are perpendicular to the control gate lines and the source lines.