a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column;

a word line driver circuit for each row having an output connected to drive the word line of the row;

a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation;

a column processing circuit connected to the at least one bit line for each column and configured to process an analog voltage developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; and

a bit line clamping circuit comprising a sensing circuit configured to compare the analog voltage on a given bit line to a threshold voltage and a voltage clamp circuit that is actuated in response to the comparison to preclude the analog voltage on that given bit line from decreasing below a clamping voltage level.