US 12,237,003 B2
Management of dynamic read voltage sequences in a memory subsystem
Yu-Chung Lien, San Jose, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,180.
Prior Publication US 2024/0046981 A1, Feb. 8, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A system comprising:
a memory component; and
a processing device, coupled with the memory component, to:
receive a first read command and a second read command;
responsive to determining that the first read command originated from a host system, selecting a reverse read trim setting from a trim register of the memory component configured to store at least two sets of trim settings including the reverse read trim setting;
responsive to determining that the second read command did not originate from the host system, selecting a forward read trim setting;
executing the first read command using the reverse read trim setting; and
executing the second read command using the forward read trim setting.