	US 12,237,002 B2
	Memory cell biasing techniques during a read operation
Andrea Locatelli, Dalmine (IT); Giorgio Servalli, Fara Gera d'Adda (IT); and Angelo Visconti, Appiano Gentile (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 10, 2022, as Appl. No. 17/741,136.
Application 17/741,136 is a continuation of application No. 16/834,941, filed on Mar. 30, 2020, granted, now 11,348,635.
Prior Publication US 2022/0270667 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4096 (2006.01); G11C 11/22 (2006.01); G11C 11/406 (2006.01); G11C 11/4091 (2006.01); G11C 11/4097 (2006.01)

CPC G11C 11/4096 (2013.01) [G11C 11/221 (2013.01); G11C 11/2273 (2013.01); G11C 11/406 (2013.01); G11C 11/4091 (2013.01); G11C 11/4097 (2013.01)]

20 Claims

1. An apparatus, comprising:

a biasing component configured to:

apply a first voltage to a digit line of a memory cell during a first phase of an access operation;

increase the first voltage to a second voltage during the first phase of the access operation;

maintain a third voltage at a plate line of the memory cell for a duration based at least in part on increasing the first voltage to the second voltage; and

initiate a second phase of the access operation based at least in part on a voltage difference between the second voltage and the third voltage.