| CPC G11C 11/4078 (2013.01) [G11C 11/40622 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cell rows, wherein each of the plurality of memory cell rows comprises a respective plurality of memory cells;
a row hammer management circuit configured to:
determine counted values by counting a number of times each of the plurality of memory cell rows are accessed in response to an active command applied at a first time point from an external memory controller;
store the counted values as count data in count cells associated with respective ones of the plurality of memory cell rows; and
in response to a precharge command applied at a second time point after a first command was applied, perform an internal read-update-write operation, wherein the internal read-update-write operation comprises reading the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, updating the count data that was read to obtain updated count data, and writing the updated count data in a respective ones of the count cells of the target memory cell row,
wherein the first command designates a memory operation on the target memory cell row, and is applied after the active command was applied; and
a control logic circuit configured to perform the memory operation on the target memory cell row based on the first command and configured to control the row hammer management circuit.
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