| CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a plurality of counters respectively corresponding to a plurality of rows, and each configured to count a number of accesses to a corresponding row among the plurality of rows;
a plurality of first flags respectively corresponding to the plurality of rows;
a queue configured to store a plurality of addresses; and
a refresh control circuit configured to:
change a second flag set in a refresh period every refresh period, and
determine whether to put an incoming row address into the queue based on:
a count value of a counter, which corresponds to a target row indicated by the incoming row address among the plurality of rows, among the plurality of counters,
a first flag value of a first flag corresponding to the target row among the plurality of first flags, and
a second flag value of the second flag set in a current refresh period.
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