| CPC G11C 11/40611 (2013.01) [G06F 12/06 (2013.01); G11C 11/406 (2013.01); G11C 11/408 (2013.01); G06F 2212/70 (2013.01)] | 20 Claims |
|
1. A memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word-lines;
an address manager circuit configured to:
receive a refresh command from a memory controller;
perform sampling on a plurality of access addresses provided from the memory controller and determine a maximum access address among the plurality of access addresses based on count values associated with each of the plurality of access addresses;
randomly determine a capture time; and
identify an access address that is provided from the memory controller at the capture time as a capture address; and
a refresh controller circuit configured to select one of the maximum access address and the capture address as a refresh address and refresh target memory cells among the plurality of memory cells based on the refresh address.
|