a first word line driver including a far section and a near section;

a second word line driver;

a plurality of independent segments of pixel drive circuits of a backplane, the plurality of independent segments of pixel drive circuits being disposed between the first word line driver and the second word line driver, the first word line driver being aligned parallel to the second word line driver; and

a plurality of display controller circuits configured to control the plurality of independent segments of pixel drive circuits, the far section and the near section are associated with separate display controllers of the plurality of display controller circuits

the plurality of independent segments of pixel drive circuits each including pixel drive circuitry corresponding with a memory element.