a display panel including pixels, the display panel also including a first display area and a second display area with the first display area being driven at a first frequency and the second display area being driven at a second frequency lower than the first frequency;

a first gate driver including first stages that output respective first carry signals; and

first buffers each coupled to a respective first stage, that output respective first gate signals, and that provide the respective first gate signals to the pixels, wherein

a first gate signal among the first gate signals output from a first buffer corresponding to the first display area among the first buffers is provided to the pixels disposed in the first display area,

a first buffer corresponding to the second display area among the first buffers does not output the first gate signal such that the first gate signal is not provided to the pixels disposed in the second display area,

at least one first buffer of the first buffers for the first display area receives a buffer clock signal having a logic-low level while simultaneously at least another first buffer of the first buffers for the second display area receives a buffer clock signal having a logic-high level, and

the logic high level of the buffer clock signal is substantially equal to a voltage level of a first driving power, and the logic low level of the buffer clock signal is substantially equal to a voltage level of a second driving power lower than the first driving power.