| CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G11C 19/28 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01)] | 14 Claims |
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1. A shift register, comprising:
a node control circuit, electrically connected to a first level signal receive end, a second level signal receive end, a first clock signal end, a second clock signal end, a first node, and a second node;
an input circuit, electrically connected to the second clock signal end, a trigger signal input end, and the second node;
a voltage regulator circuit, electrically connected to the second node, the second clock signal end, and a third node; and
an output circuit, electrically connected to the first level signal receive end, the second level signal receive end, the first node, the third node, and a drive signal output end;
wherein the input circuit is configured to receive an input signal of the trigger signal input end, and control a signal of the second node in response to a second clock signal received by the second clock signal end;
wherein the node control circuit is configured to receive a first level signal received by the first level signal receive end and a second level signal received by the second level signal receive end, and control a signal of the first node in response to the signal of the second node, a first clock signal received by the first clock signal end, and the second clock signal received by the second clock signal end;
wherein the output circuit is configured to:
receive the second level signal received by the second level signal receive end, and control, in response to the signal of the first node, a signal output by the drive signal output end; or
receive the first level signal of the first level signal receive end, and control, in response to a signal of the third node, a signal output by the drive signal output end;
wherein the voltage regulator circuit is configured to receive the signal of the second node, and control the signal of the third node in response to the second clock signal received by the second clock signal end;
wherein the first level signal is a low level signal, the second level signal is a high level signal, and when the signal output by the drive signal output end is a low level signal, a potential of the signal of the third node is less than a potential of the first level signal received by the first level signal receive end;
wherein the node control circuit comprises at least one transistor whose active layer is an oxide semiconductor, and at least one of the input circuit, the voltage regulator circuit, or the output circuit comprises at least one transistor whose active layer is silicon;
wherein the voltage regulator circuit comprises a seventh transistor and a first capacitor; and
wherein a gate of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the first clock signal end, a second electrode of the seventh transistor is electrically connected to a second electrode of the first capacitor, and a first electrode of the first capacitor is separately electrically connected to the third node and the second node.
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