US 12,236,890 B2
Shift register, driving method thereof, display substrate and display device
Yao Huang, Beijing (CN); Juntao Chen, Beijing (CN); and Juan Fang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/033,365
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 27, 2022, PCT No. PCT/CN2022/095644
§ 371(c)(1), (2) Date Apr. 24, 2023,
PCT Pub. No. WO2023/226010, PCT Pub. Date Nov. 30, 2023.
Prior Publication US 2024/0379061 A1, Nov. 14, 2024
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register comprising a first control sub-circuit, a second control sub-circuit, a pull-up control sub-circuit and an output control sub-circuit, wherein the shift register is electrically connected to a signal input terminal, a signal output terminal, a clock signal terminal and a first power supply terminal through a third power supply terminal;
the first control sub-circuit, electrically connected to the signal input terminal, the clock signal terminal, the third power supply terminal, a first node, a second node and a third node respectively, is configured to provide a signal of the third power supply terminal or the clock signal terminal to the first node and the third node under the control of the signal input terminal, the clock signal terminal and the second node;
the pull-up control sub-circuit, electrically connected to the second power supply terminal, the first node and the third node respectively, is configured to provide a signal of the second power supply terminal to the first node under the control of the third node;
the second control sub-circuit, electrically connected to the clock signal terminal, the signal input terminal, the first power supply terminal, the second node and a fourth node respectively, is configured to provide a signal of the signal input terminal to the second node and the fourth node under the control of the clock signal terminal and the first power supply terminal; and
the output control sub-circuit, electrically connected to the signal output terminal, the first power supply terminal, the third power supply terminal, the first node and the fourth node respectively, is configured to provide a signal of the first power supply terminal or the signal of the third power supply terminal to the signal output terminal under the control of the first node and the fourth node.