US 12,236,872 B2
Display panel and display device
Qingjun Lai, Xiamen (CN); Yihua Zhu, Xiamen (CN); Jinjin Yang, Xiamen (CN); and Ping An, Xiamen (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Mar. 13, 2023, as Appl. No. 18/183,112.
Application 18/183,112 is a continuation of application No. 17/512,683, filed on Oct. 28, 2021, granted, now 11,626,069.
Claims priority of application No. 202110536427.3 (CN), filed on May 17, 2021.
Prior Publication US 2023/0222979 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/061 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a drive module, a compensation module and a reset module, wherein,
the drive module comprises a drive transistor;
the reset module is configured to provide a reset signal for a gate of the drive transistor, wherein the reset module comprises a first double-gate transistor, the first double-gate transistor comprises a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node;
the compensation module is connected between the gate of the drive transistor and a drain of the drive transistor, and the compensation module comprises a second double-gate transistor, the second double-gate transistor comprises a third sub-transistor and a fourth sub-transistor, and a connection node between the third sub-transistor and the fourth sub-transistor is a third node;
the pixel circuit is connected to a first power supply voltage signal terminal, and is configured to receive a first power supply voltage signal, and the first power supply voltage signal is a high level signal;
the pixel circuit comprises a first capacitor, a first pole plate of the first capacitor is connected to the first power supply voltage signal terminal, and a second pole plate of the first capacitor is connected to the second node;
a gate of the first double-gate transistor is connected to a line of first scan signal, and is configured to receive a first scan signal, wherein the pixel circuit comprises a second capacitor, a first pole plate of the second capacitor is connected to the line of first scan signal, and a second pole plate of the second capacitor is connected to the second node;
a gate of the second double-gate transistor is connected to a line of second scan signal, and is configured to receive a second scan signal, wherein the pixel circuit comprises a third capacitor, a first pole plate of the third capacitor is connected to the line of second scan signal, and a second pole plate of the third capacitor is connected to the third node;
capacitance of the second capacitor (C2) is less than or equal to capacitance of the third capacitor (C3); and
capacitance of the first capacitor (C1) is greater than capacitance of the second capacitor (C2).