US 12,236,869 B2
Display panel and display device
Lihua Wang, Shenzhen (CN); Yuheng Zhang, Shenzhen (CN); Qiongqin Mao, Shenzhen (CN); Yang Nan, Shenzhen (CN); Tingling Li, Shenzhen (CN); and Yimiao Ding, Shenzhen (CN)
Assigned to TIANMA MICROELECTRONICS CO., LTD., Shenzhen (CN)
Filed by TIANMA MICROELECTRONICS CO., LTD., Shenzhen (CN)
Filed on Oct. 17, 2022, as Appl. No. 17/967,086.
Claims priority of application No. 202210773012.2 (CN), filed on Jun. 30, 2022.
Prior Publication US 2023/0042146 A1, Feb. 9, 2023
Int. Cl. G09G 3/3233 (2016.01); H01L 25/075 (2006.01); H01L 29/786 (2006.01)
CPC G09G 3/3233 (2013.01) [H01L 25/0753 (2013.01); H01L 29/78648 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2330/021 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising a pixel driver circuit; wherein,
the pixel driver circuit comprises a light-emitting module, a drive transistor and at least one light-emitting control transistor;
the drive transistor, the at least one light-emitting control transistor and the light-emitting module are connected in series between a first power supply signal terminal and a second power supply signal terminal;
the drive transistor is configured to drive the light-emitting module to emit light in a light-emitting stage;
the at least one light-emitting control transistor is configured to provide drive current generated by the drive transistor to the light-emitting module in the light-emitting stage;
at least one of the drive transistor or a light-emitting control transistor of the at least one light-emitting control transistor is a first double-gate transistor; and
the first double-gate transistor comprises a first gate, a second gate and a first source, and the second gate is electrically connected to the first source,
wherein at least one of the drive transistor or the light-emitting control transistor is a second double-gate transistor; and
the second double-gate transistor comprises a third gate and a fourth gate, and the third gate is electrically connected to the fourth gate,
wherein the first double-gate transistor comprises a plurality of first double-gate sub-transistors, and the plurality of first double-gate sub-transistors are connected in parallel, and
wherein the second double-gate transistor comprises a plurality of second double-gate sub-transistors, and the plurality of second double-gate sub-transistors are connected in parallel.