| CPC G09G 3/20 (2013.01) [G11C 19/287 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
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1. A shift register, comprising:
an input sub-circuit connected to an input terminal of the shift register and a pull-up node of the shift register, wherein the input-sub-circuit is configured to provide a signal of the input terminal to the pull-up node;
an output sub-circuit connected to the pull-up node, a clock signal terminal of the shift register, and an output terminal of the shift register, wherein the output sub-circuit is configured to provide a signal of the clock signal terminal to the output terminal under the control of a potential of the pull-up node; and
a control sub-circuit connected to the pull-up node, the output terminal, and a pull-down node of the shift register, wherein the control sub-circuit is configured to control a potential of the pull-down node based on the potential of the pull-up node, and pull down a potential of the output terminal under the control of the potential of the pull-down node;
wherein the output sub-circuit comprises a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit, the clock signal terminal comprises a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, and the output terminal comprises a first output terminal, a second output terminal, and a third output terminal;
wherein the first output sub-circuit comprises a first transistor, a gate electrode of the first transistor is connected to the pull-up node, a first electrode of the first transistor is connected to the first clock signal terminal, and a second electrode of the first transistor is connected to the first output terminal;
wherein the second output sub-circuit comprises a second transistor and a first capacitor, a gate electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the second clock signal terminal, a second electrode of the second transistor is connected to the second output terminal, a first electrode of the first capacitor is connected to the gate electrode of the second transistor, and a second electrode of the first capacitor is connected to the second electrode of the second transistor;
wherein the third output sub-circuit includes a third transistor and a second capacitor, a gate electrode of the third transistor is connected to the pull-up node, a first electrode of the third transistor is connected to the third clock signal terminal, a second electrode of the third transistor is connected to the third output terminal, and a first electrode of the second capacitor is connected to the gate electrode of the third transistor, a second electrode of the second capacitor is connected to the second electrode of the third transistor, wherein each of the second output terminal and the third output terminal is configured to connect with a sub pixel to apply a gate drive signal to the sub pixel, and the first output terminal is configured to connect with another shift register to achieve cascading with the another shift register; and
wherein the control sub-circuit includes a first control sub-circuit and a second control sub-circuit, the first control circuit is electrically connected to the pull-up node, the first output terminal, and the second output terminal, and the second control sub-circuit is electrically connected to the pull-up node, the first output terminal, and the third output terminal.
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