| CPC G06T 15/06 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06T 1/60 (2013.01); G06T 5/70 (2024.01); G06T 9/00 (2013.01); G06T 2207/20081 (2013.01); G06T 2210/08 (2013.01)] | 30 Claims |
|
1. A system comprising:
a Peripheral Component Interconnect Express interface;
a set of memory controllers;
a plurality of multi-core groups coupled to the Peripheral Component Interconnect Express interface and the set of memory controllers, wherein a multi-core group within the plurality of multi-core groups comprises:
a plurality of graphics cores to process one or more shader programs;
a plurality of tensor cores, apart from the plurality of graphics cores, to perform matrix operations;
a ray tracing core, apart from the plurality of graphics cores and the plurality of tensor cores, to perform bounding volume hierarchy (BVH) operations and triangle intersection operations;
a first cache shared among the plurality of graphics cores, the plurality of tensor cores, and the ray tracing core; and
a set of register files to store operand values;
wherein execution circuitry of at least one of the plurality of graphics cores, the plurality of tensor cores, and the ray tracing core is to execute a first instruction to select a minimum value from a plurality of threads, the first instruction including a first operand identifying values within the plurality of threads, and wherein the execution is to perform:
returning a minimum value from values within a set of threads, the set of threads selected from the plurality of threads based on a mask; and
a second cache shared by the plurality of multi-core groups.
|