| CPC G06F 9/466 (2013.01) [G06F 9/54 (2013.01); G06F 2209/543 (2013.01)] | 20 Claims |
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1. A system comprising:
a plurality of source nodes configured to issue transactions;
a plurality of address decoders, each address decoder associated with a respective source node from the plurality of source nodes;
one or more interconnects coupled to the plurality of address decoders; and
a plurality of target nodes coupled to the one or more interconnects,
wherein each address decoder from the plurality of address decoders comprises:
a memory configured to store an internal configuration for the address decoder;
a decode windows selection circuit coupled to the memory, and having a decode windows selection circuit output configured to output a set of decode windows based on the internal configuration, wherein the set of decode windows corresponds to a set of target nodes in the plurality of target nodes that a source node associated with a given address decoder is allowed to access;
a decode method selection circuit coupled to the memory, and having a decode method selection circuit output configured to output a determination of a target node associated with a decode method for a transaction issued by the source node based on the internal configuration and the set of decode windows; and
a target identifier (ID) generation circuit coupled to the memory and the decode method selection circuit, and having a target ID generation circuit output configured to output a target node ID associated with the target node of the decode method, wherein the target node ID is used to route the transaction to the target node, and
wherein the one or more interconnects are configured to direct the transaction to the target node based on the target node ID.
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