US 12,236,246 B2
Modular, extensible computer processing architecture
Ioannis Karageorgos, New Haven, CT (US); Karthik Sriram, New Haven, CT (US); Jan Vesely, Hamden, CT (US); Rajit Manohar, New Haven, CT (US); and Abhishek Bhattacharjee, New Haven, CT (US)
Assigned to Yale University, New Haven, CT (US)
Filed by Yale University, New Haven, CT (US)
Filed on Dec. 8, 2020, as Appl. No. 17/115,195.
Claims priority of provisional application 62/947,795, filed on Dec. 13, 2019.
Prior Publication US 2021/0182073 A1, Jun. 17, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 1/10 (2006.01); G06F 3/01 (2006.01); G06F 9/48 (2006.01); G06F 13/40 (2006.01); G06F 17/14 (2006.01)
CPC G06F 9/3871 (2013.01) [G06F 1/10 (2013.01); G06F 3/015 (2013.01); G06F 9/4881 (2013.01); G06F 13/4022 (2013.01); G06F 17/142 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A computer processing architecture comprising:
a plurality of processing elements, each processing element configured to:
receive a set of data from one or more input channels or from another processing element;
execute at least one of a plurality of individualized processes on the data, distinct from processes of other processing elements of the plurality of processing elements; and
output the processed data according to an independent clock domain of the processing element, at least some of which are distinct from other clock domains;
a plurality of switches, wherein each switch connects a processing element to an input channel of the one or more input channels or to another processing element; and
a micro-controller configured to:
receive the processed data;
control the plurality of switches by activating or deactivating each switch;
generate a pipeline of processing elements from activating and deactivating the plurality of switches; and
select one or more individualized processes of the plurality of individualized processes that each processing element within the pipeline executes;
wherein the plurality of processing elements are not general purpose central processing units (CPUs), graphics processing units (GPUs), or single instruction, multiple data (SIMD) processing units; and
wherein the pipeline operates within a 15 mW power budget.