CPC G06F 9/30145 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a plurality of memory controllers;
a cache memory coupled to the plurality of memory controllers; and
a processor coupled to the plurality of memory controllers, and coupled to the cache memory, the processor having a plurality of cores, including a core to perform operations corresponding to an instruction identifying two two-dimensional source tiles in memory, the two two-dimensional source tiles including a first two-dimensional source tile and a second two-dimensional source tile, the operations including to:
determine that an indicator indicates that the two two-dimensional source tiles are to be loaded; and
load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile.
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