| CPC G06F 9/30098 (2013.01) [G06F 9/3824 (2013.01); G06F 9/3826 (2013.01); G06F 9/3869 (2013.01); G06F 15/8023 (2013.01)] | 18 Claims |
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1. A data processing apparatus, comprising:
operand routing hardware circuitry configured to prepare operands for processing;
a group of coupled processing elements, each processing element in the group of coupled processing elements comprising receiving hardware circuitry configured to receive operands, processing hardware circuitry configured to perform processing operations based on the received operands, and transmitting hardware circuitry configured to transmit a subset of the received operands to a further processing element,
wherein the group of coupled processing elements comprises a first processing element configured to receive operands from the operand routing hardware circuitry, and the group of coupled processing elements comprises one or more further processing elements, wherein receiving hardware circuitry for each of the one or more further processing elements is coupled to transmitting hardware circuitry of another processing element in the group of coupled processing elements, such that the group of coupled processing elements is arranged to perform processing operations which take as inputs one or more input operands wherein each of the one or more input operands is initially received from the operand routing hardware circuitry at the first processing element;
the group of coupled processing elements comprises timing hardware circuitry, configured to selectively delay transmission of operands within the group of coupled processing elements to cause operations performed by the group of coupled processing elements to be staggered; and
the group of coupled processing elements comprises operand selection hardware circuitry; wherein
operand selection hardware circuitry for a given processing element in the group of coupled processing elements is configured to perform a selection of a selected subset of the operands received at receiving hardware circuitry of the given processing element, wherein the selected subset of the operands are operands to be used in a processing operation performed by processing hardware circuitry of the given processing element.
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