US 12,236,220 B2
Flow control for reconfigurable processors
Weiwei Chen, Palo Alto, CA (US); Raghu Prabhakar, San Jose, CA (US); David Alan Koeplinger, Egg Harbor, NJ (US); Sitanshu Gupta, Palo Alto, CA (US); Ruddhi Chaphekar, Palo Alto, CA (US); Ajit Punj, Palo Alto, CA (US); and Sumti Jairath, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jun. 7, 2023, as Appl. No. 18/206,829.
Application 18/206,829 is a continuation of application No. 16/890,841, filed on Jun. 2, 2020, granted, now 11,709,664.
Prior Publication US 2023/0325163 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 8/41 (2018.01); G06F 15/78 (2006.01); G06F 15/82 (2006.01)
CPC G06F 8/452 (2013.01) [G06F 8/41 (2013.01); G06F 15/7867 (2013.01); G06F 15/825 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A computer-implemented method, including:
executing a dataflow graph on a processing system having a plurality of compute nodes, each having a ready-to-read credit counter and a write credit counter, that transmit data along data connections; and
controlling data transmission between compute nodes in the plurality of compute nodes along the data connections by using dedicated control connections between the compute nodes to selectively control writing of data based on both the ready-to-read credit counter and the write credit counter in a particular compute node of the plurality of compute nodes that provides the data for a particular data transmission, wherein the control connections are distinct from the data connections and are configured to transmit control signals that manage flow of the data by selectively incrementing the ready-to-read credit counter and the write credit counter in the particular compute node.