US 12,236,209 B2
Processing element, neural processing device including same, and multiplication operation method using same
Jaewan Bae, Seongnam-si (KR); Jinwook Oh, Seongnam-si (KR); and Karim Charfi, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Nov. 16, 2023, as Appl. No. 18/511,942.
Application 18/511,942 is a continuation of application No. 17/807,082, filed on Jun. 15, 2022, granted, now 11,868,741.
Claims priority of application No. 10-2021-0078867 (KR), filed on Jun. 17, 2021; and application No. 10-2022-0066221 (KR), filed on May 30, 2022.
Prior Publication US 2024/0086150 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/533 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/533 (2013.01) [G06F 7/5443 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing circuitry comprising:
a weight register configured to store a weight;
an input activation register configured to store an input activation;
first and second multiplier circuits configured to generate partial multiplication groups by performing a multiplication operation of the weight stored in the weight register and the input activation stored in the input activation register;
a digital aligning circuit configured to generate a first aligned partial multiplication group and a second aligned partial multiplication group by aligning first and second partial multiplication groups with same number of digits wherein the first aligned partial multiplication group is calculated by using a first booth reduction tree and the second aligned partial multiplication group is calculated by using a second booth reduction tree;
first and second adder circuits configured to generate result data by using one of the partial multiplication groups or one of the first and the second aligned partial multiplication groups; and
a third adder circuit configured to generate a partial sum by using the result data.