US 12,236,180 B2
Integrated circuit and method of manufacturing the same
Yu-Jung Chang, Hsinchu (TW); Chin-Chang Hsu, Hsinchu (TW); Hsien-Hsin Sean Lee, Duluth, GA (US); and Wen-Ju Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,771.
Application 18/446,771 is a division of application No. 17/494,704, filed on Oct. 5, 2021, granted, now 11,775,724.
Application 17/494,704 is a division of application No. 16/695,047, filed on Nov. 25, 2019, granted, now 11,138,361, issued on Oct. 5, 2021.
Application 16/695,047 is a division of application No. 15/861,128, filed on Jan. 3, 2018, granted, now 10,489,548, issued on Nov. 26, 2019.
Claims priority of provisional application 62/511,847, filed on May 26, 2017.
Prior Publication US 2023/0385511 A1, Nov. 30, 2023
Int. Cl. G06F 30/392 (2020.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/118 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01)
CPC G06F 30/392 (2020.01) [H01L 21/28008 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 27/11807 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for manufacturing an integrated circuit, the system comprising:
a non-transitory computer readable medium configured to store executable instructions; and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the executable instructions for:
placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each layout pattern of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction and overlapping a set of gridlines, the set of gridlines extending in the second direction, and each gridline of the set of gridlines being separated from an adjacent gridline of the set of gridlines by the first pitch, wherein the set of gate layout patterns includes:
a first set of gate layout patterns corresponding to fabricating a set of functional gate structures of the integrated circuit; and
a second set of gate layout patterns corresponding to fabricating a set of non-functional gate structures of the integrated circuit; and
generating a cut feature layout pattern extending in the first direction, the cut feature layout pattern being on the first layout level, and overlapping each of the layout patterns of the set of gate layout patterns at a same position in the second direction, the cut feature layout pattern identifying a location of a removed portion of a gate structure of the set of gate structures.