a first memory cell array that includes a plurality of first blocks, each first block including a plurality of first memory cells, each of the first memory cells capable of being set into one of n threshold voltage levels, n being an integer of 4 or more;

a plurality of first word lines, each first word line being connected to a gate of a corresponding one of the first memory cells in each of the first blocks;

a plurality of first bit lines electrically connected to one ends of the first memory cells of each first block, respectively;

a plurality of first sense amplifiers connected to the first bit lines, respectively;

a second memory cell array that includes a plurality of second blocks, each second block including a plurality of second memory cells, each of the second memory cells capable of being set into one of n threshold voltage levels;

a plurality of second word lines, each second word line being connected to a gate of a corresponding one of the second memory cells in each of the second blocks;

a plurality of second bit lines electrically connected to one ends of the second memory cells of each second block, respectively; and

a plurality of second sense amplifiers connected to the second bit lines, respectively, wherein

upon receipt of a first read command associated with a first address,

upon receipt of a second read command associated with a second address,