N planes each including a plurality of memory cells;

a signal generation block suitable for:

selecting a control code corresponding to N selection values from N control codes respectively corresponding to the N planes, and

generating an operation control signal by decoding the selected control code;

N operation performing blocks each suitable for performing a predefined operation on a corresponding plane of the N planes according to a value of the operation control signal;

a signal transmission block suitable for transmitting the operation control signal to one of the N operation performing blocks through a path corresponding to the N selection values among N paths that connect the signal generation block to the respective N operation performing blocks; and

a selection control block suitable for activating at each time an input clock becomes a predetermined logic level, one of the N selection values, while deactivating remaining N selection values,

wherein the signal transmission block includes:

N signal storage units;

N storage control units suitable for storing the operation control signal in the respective N signal storage units during activation periods of the respective N selection values; and

N operation transmission units suitable for:

generating an operation execution signal according to the value of the operation control signal outputted by the respective N signal storage units during a predetermined period after deactivation of the respective N selection values, and

transmitting the operation execution signal to the respective N operation performing blocks through the respective N paths, where “N” is a natural number equal to or greater than 2.