| CPC G06F 3/0659 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0656 (2013.01); G06F 3/0683 (2013.01)] | 11 Claims |
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1. A processor configured to perform a predetermined computational operation in which one or more data elements is used to determine a result, the processor comprising:
one or more processor cores;
at least one buffer memory;
wherein the processor is connectable to a main memory, and being configured to access the main memory if the main memory is connected, each processor core being configured to execute instructions;
wherein the at least one buffer memory includes a calculation circuit configured to execute the computational operation in response to an execution signal if the one or the multiple data elements is stored in the buffer memory, the result being stored in the at least one buffer memory; and
wherein the processor is configured to perform the computational operation optionally using one of the processor cores using instructions or in the at least one buffer memory using the calculation circuit, wherein a decision whether the computational operation is performed using one of the processor cores or in the at least one buffer memory is based on an expected reusability degree of the one or more data elements and/or of the result.
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