US 12,236,130 B2
Address hashing in a multiple memory controller system
Steven Fishwick, St. Albans (GB); Lior Zimet, Haifa (IL); and Harshavardhan Kaushikkar, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 16, 2023, as Appl. No. 18/318,672.
Application 18/318,672 is a continuation of application No. 17/353,349, filed on Jun. 21, 2021, granted, now 11,693,585.
Claims priority of provisional application 63/179,666, filed on Apr. 26, 2021.
Prior Publication US 2023/0367510 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0871 (2016.01); G06F 12/0882 (2016.01); G06F 12/1018 (2016.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0611 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 12/0238 (2013.01); G06F 12/0646 (2013.01); G06F 12/0871 (2013.01); G06F 12/0882 (2013.01); G06F 12/1018 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of memory controllers configured to control access to memory devices;
a plurality of hardware agent circuits configured to access data in the memory devices using memory addresses, wherein:
the memory addresses are defined within a memory address space that maps memory addresses to memory locations in the memory devices,
a given memory address in the memory address space uniquely identifies a memory location in one of the memory devices coupled to one of the plurality of memory controllers, and
a given page within the memory address space is divided into a plurality of blocks that are distributed over two or more of the plurality of memory controllers;
a communication fabric coupled to the plurality of memory controllers and the plurality of hardware agent circuits, wherein:
the communication fabric is configured to route a first memory request having a first memory address to a first memory controller of the plurality of memory controllers based on the first memory address, and
interconnect circuitry in the communication fabric is configured to hash address bits of the first memory address to direct the first memory request to the first memory controller at a plurality of levels of granularity; and
a plurality of configuration registers having a plurality of fields corresponding to respective levels of the plurality of levels of granularity, wherein the plurality of fields are programmed to map the plurality of blocks of a given page at the respective levels of granularity, wherein the interconnect circuitry is configured to hash selected ones of the address bits of a given memory address for a respective level of granularity based on data in corresponding fields of a particular one of the plurality of configuration registers.