CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/1636 (2013.01); G06F 13/1689 (2013.01); G06Q 10/00 (2013.01); G06Q 20/00 (2013.01); G11C 7/02 (2013.01); G11C 11/406 (2013.01); G11C 11/40611 (2013.01); G11C 11/40615 (2013.01); G11C 11/40618 (2013.01); G11C 2211/4061 (2013.01)] | 20 Claims |
1. A memory controller to control a dynamic random access memory device (DRAM) that includes a data interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
command logic to generate a refresh command, wherein the refresh command includes a plurality of bits that specify that the DRAM perform an internal refresh operation to refresh data stored in at least one bank of the plurality of memory banks; and
a command interface to transmit the refresh command to the DRAM, wherein the refresh command includes an operation code to enable calibration of the data interface of the DRAM in parallel with the internal refresh operation.
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